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A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
| Publication type | Journal paper |
|---|---|
| Year of publication | 2008 |
| Authors | Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, and Andrea Scorzoni |
| Title | A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver |
| Journal title | Integration, the VLSI Journal |
| Volume | 41 |
| Issue | 2 |
| Pages | 161–170 |
| Editor | |
| Publisher | Elsevier |
| Date | February 2008 |
| Place | |
| ISSN number | 0167-9260 |
| ISBN number | |
| Key words | Viterbi decoder, Software defined radio, Field Programmable Gate Array (FPGA), Configurable and programmable architecture |
| Abstract | This paper presents a Viterbi decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a software defined radio (SDR) mobile transceiver, reconfigurable on request and capable to provide agility in choosing between different standards. UMTS and GPRS Viterbi decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of programmability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA for providing a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupancy of 46%, due to the efficient resources reuse. |
| URL | http://www.sciencedirect.com/science?_ob=ArticleURL&_udi=B6V1M-4NGKVBC-1&_user=10&_coverDate=04%2F13%2F2007&_rdoc=1&_fmt=&_orig=search&_sort=d&view=c&_acct=C000050221&_version=1&_urlVersion=0&_userid=10&md5=e43a75f2da9b9183091e9d5a7ab0ff99 |
| DOI | http://dx.doi.org/10.1016/j.vlsi.2007.04.001 |
| Other information | |
| Paper |  (portable document format, 926029 Bytes) |