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Implementation of a Reprogrammable DSP/FPGA Based Platform for Real-Time HD Video Coding

Publication typeConference paper
Year of publication2010
AuthorsFederico Fiorucci, Ludovico Verducci, Paolo Micanti, Giuseppe Baruffa, and Fabrizio Frescura
TitleImplementation of a Reprogrammable DSP/FPGA Based Platform for Real-Time HD Video Coding
Conference name4th European DSP Education and Research Conference (EDERC 2010)
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Publisher
DateDecember 2010
PlaceNice, France
ISSN number
ISBN number9780955204746
Key wordsJPWL, H.264, JPEG 2000, DSP, FPGA
AbstractIn this paper we present the architecture of a DSP/FPGA based hardware platform, conceived to leverage programmable logic processing power for high definition video processing. The system is reconfigurable and scalable, since multiple boards may be parallelized to speed-up the most demanding tasks. JPEG 2000 and H.264, both at HD and Super HD resolutions, have been simulated and their performance found on the embedded processing cores. The TI TMS320C6455 DSP has been selected for the instruction set dedicated to Galois field arithmetic, used in the JPWL standard. The results show that real-time, or near real-time, encoding is viable, and the modularity of the architecture allows for parallelization and performance scalability.
URLhttp://www.ti.com/ww/eu/EDERC2010/ederc2010.html?DCMP=uni_ederc2010&HQS=NotApplicable+OT+ederc2010
DOI
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Last update: 2015-10-12, 16:44:51