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CDMA satellite modem


A CDMA modem gives the ability to each user to transmit in the same frequency band simultaneously so the channel can be easily managed. The CDMA technique allows a dynamic resources allocation so it is very attractive to implement a device which can be used for different kinds of services (voice, video, data). A possible scenario is depicted in figure 1: four earth stations (Universities' sites) are connected through the satellite repeater, and they can communicate using the CDMA modem.


The main functions, and technical characteristics of the DSP based CDMA modem are summarized in the following items:

  • The modem has 6 full-duplex channels, each with 64 Kb/s throughput (altogether 384 Kb/s).
  • The PC interface is implemented through a PCI or a USB controller. The spreading factor is 63, so each channel occupies about a 4.12 MHz frequency band.
  • The GOLD codes have been chosen since they have good cross correlation properties.
  • The BER performance is guaranteed by a convolutional encoder/Viterbi decoder.
  • The channel can be modelled as a single ray AWGN since it is a satellite channel.
  • The FPGA implements the symbol generation and the base band aggregation of the 6 channels.

As you can see in figure 2, the hardware architecture can essentially be subdivided in two main sections:

  • A custom devices section.
  • A DSP section.

The ASIC side is made up by a convolutional encoder/Viterbi decoder chip and a Spread Spectrum Transceiver (SS TXR) chip in each one of the six channels. The SS TXR affords full duplex communication, but its performance is poor when CDMA technique is requested, since the receiver is a conventional single user.

The DSP side is made up by 12 DSPs, 2 for each one of the 6 channels. This high processing capacity (3200 MIPS/each channel if the DSP is a 'C6201) allows it implementing various kinds of multi user detection (MUD) algorithms. In this manner we can have better performance than the ASIC side and a CDMA multiple access protocol is really feasible. In the first developing stage, the performance of the ASIC side, in terms of SNR at the receiver, will be compared with the MUD algorithms on the DSPs. When these algorithms will give a better SNR, the ASIC side will work as transmitter, while the receiver is implemented by DSPs through MUD algorithms. After the MUD algorithms will be tested, we no larger need the SS TXR and we could substitute the ASICs with 2 DSPs: that make up the transmitter section. At the final design stage, the MODEM is constituted only by TI DSPs, both at the transmitting and the receiving section.

The most amazing idea is to design the DSP side section through modular units which can be easily expanded when the requested CPU performance has to be improved. The functional block diagram represented in figure 3 illustrates the hardware architecture of a single channel receiver implemented with TI DSPs. Other channels can be added by repeating this structure. The microcontroller manages the DSP boot, transferring the firmware from the FLASH memory to the DSPs' program RAM. The SBS-RAM is used as external memory by the microcontroller, while the dual port ram memories allow a high speed data exchange between the DSPs.


An high speed throughput is feasible between the DSP2 and the microcontroller using the dual port 32 bit SRAM1 working at 50 MHz. The serial communications are enabled through the McBSP on the 'C6000 DSP and the microcontroller. The two DSPs can exchange data employing an high performance dual port 32 bit SRAM @ 200MHz. The DP-SRAM1 can be used as buffer data among the m-controller and DSPs, when these ones share the 2nd port. Then the m-controller becomes the memory access arbiter, by giving one read-write permission at a time to the DSPs. This architecture can be expanded in two ways:


  • Adding DSP1, DSP2 and DP-SRAM2
  • Adding DSP1, DSP2, DP-SRAM1, and DP-SRAM2.

In the first case the DP-SRAM1 is shared by more channels, while in the second case, this module is repeated, by eliminating the access arbiter troubles, but otherwise slowing the data exchange performance among different channel DSPs. In both mentioned situations, the added devices are connected to the main bus,thus increasing the bus switch elements. In summary we can say that the architecture gives the ability to implement algorithms which require high processing performance inaddition the expansibility feature allows it increasing the overall bit-rate throughput.


Last update: 2014-11-15, 00:30:49