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Software Radio systems


Software radio (SWR) [1] is a key technology in the wireless communications industry. One of the main challenges in this market is the integration of multiple systems and applications on a single terminal. Since existing wireless communication standards are mainly adopted in a regional scale, problems arise when dealing with roaming users or different markets. Software radio allows it developing transceivers that operate with several standards and in several frequency bands on a common hardware platform. This technology is expected to be leading in several emerging application scenarios of wireless communications, including not only cellular telephony, but also in the wireless networking and in the new digital broadcasting and interactive services.

The University of Perugia has been studying software and hardware DSP based architectures in order to design a software radio development system, i.e. a completely DSP based digital radio transceiver, in which software radio algorithms can be tested. A similar idea is proposed in [2] but it is mainly optimized for military voice and data applications. Although the project includes hardware design, the main interest is focused on software issues. In this framework the study concers the integration of GSM / IS95 and UMTS / WCDMA in the cellular telephony market, IEEE 802.11, HIPERLAN and Bluetooth, in the WLAN market, and DAB, DVB and DTV in the broadcasting area. Since the above mentioned application areas require different processing capabilities and power consumption, the analysis is carried out by developing a software radio board based on both C5000 or C6000 devices as shown in figure 1.


According to this architecture, and depending on the required computational complexity, the transceiver is made-up of a certain number of standard modules, called BPU (Basic Processing Unit). The BPU contains a C5000 or a C6000 devices, each with a proper amount of dedicated external RAM. Every BPU can perform some processing functions (e.g. source coding/decoding, channel coding/decoding modulation/demodulation) and these functions are performed by the C5000 or the C6000 device depending on the standard implemented. For handheld and portable standard we are going to use TMS320C55x device which cuts down power consumption to 0.05 mW/MIPS at 0.9V. Moreover the core of TMS320C55x device suits wholly to the standards processing requirement. When the computational cost of the standard implemented are not covered with TMS320C55x we are going to use TMS320C64x device which has more MIPS. The BPU based on TMS320C55x and TMS320C64x can be swhitched in the main-board without problem, thanks to the same Bus Interface implementation. Therefore BPU operation and synchronization can be managed by the microcontroller and monitored by the JTAG connectors.

This kind of modular hardware configuration allows it designing and testing a wide range of software radio algorithms for different standards, simply varying the number of BPUs in both the transmitter and the receiver side and updating the microcontroller software. Thus, the whole complexity of the transceiver design is moved to the software side. In the framework of the integration of a pool of standards in one common hardware platform, the following issues are explored in the software area:

  • Which algorithm configuration is more efficient in terms of code size and speed.
  • Which standard is more critical in the computational cost.
  • Which functional blocks of different standards may be efficiently integrated.
  • Which family (C5000 or C6000) is more efficient in a specific design

Architecture optimization for handheld and portable application

Battery powered handheld and portable devices (i.e. a GSM / IS95 UMTS / WCDMA Bluetooth terminal) have critical power and space constraints, so their SWR architecture must be optimized with respect to these aspects. For battery powered applications, a commonly accepted SWR architecture adopts a RF receiver based on pass-band superheterodyne with a signal digitalization at IF or a direct conversion (zero IF or homodyne) configurations and all the digital processing is carried out by a flexible ASIC-DSP module (fig. 2).


In this architecture the ASIC implements functions with very high processing demand and simple algorithm structure (e.g. correlators, high speed FIR filters), while the DSP implements the more complex but less processing demanding functions (e.g. source coding/ decoding; channel coding/ decoding; interleaving/ deinterleaving). Moreover, since the DSP accesses the ASIC resources, it is able to manage the ASIC configuration and operation for the different telecommunications standard implemented.

While this configuration optimizes performance with respect to the power consumption and space constraints, it represents only an approximation of an ideal SWR design. This means that, in order to obtain the required flexibility, the ASIC must be designed to perform different (but fixed) functions that are selected and configured by the DSP core.

The hardware and software architecture can address these issues. In particular the proposed modular hardware structure allows it integrating an FPGA based BPU (Basic Processing Unit) with proper interfaces with the DSP modules. The FPGA based BPU can be considered as a valid prototype of a new ASIC layout, so different low power SWR configurations may be designed and evaluated. For low power applications the proposed SWR development system is configured as shown in fig. 3.


In order to optimize the performance of the SWR architecture with respect to space and power consumption constraints, a design process that compares optimal (as regard a specified reference hardware structure) and sub optimal implementations is being performed. In particular we take care of the following aspects:

- The number of bit in the ADC and DAC converters and in the ASIC.

ADCs show a near exponential relationship between increased resolution and dissipated power. Also ASIC area and power consumption are a polynomial function of the number of bits. This means that the choice of the ADC/DAC resolution must account for a trade-off between the requirements of different telecommunications standards implemented and the power control and AGC subsystems complexity.

- The splitting of processing functions between the ASIC and the DSP.

A key aspect for the optimization is represented by the proper assignment of the processing functions between the ASIC and DSP; implementing functions on ASIC, that can be run-time configured to support a range of telecommunications standards, does not always help reducing space and power consumption, since different functions correspond to increased ASIC area. Moreover the number of functions performed by the DSP should be maximized in order to maintain an high degree of flexibility.

- The impact on the radio performance of different sub optimal algorithms.

In portable applications all the power for transmission and signal processing is provided by the batteries, so both consumption requirements must be minimized. This means that any sub optimal algorithm must be carefully evaluated in terms of performance degradation with respect to the ideal case, because this degradation leads directly to increased power requirement for transmission and/or to a reduced sensitivity of the receiver.

The comparison of optimal and sub optimal design is being carried out according to some development guidelines as shown in the flowchart of fig. 4. Following these criteria we define a Cost Function F that comprises different parameters (with proper weights) as overall power consumption (processing + transmission), chip area (estimated by the used FPGA area for a given implementation), computational complexity (in the DSP), cost of components and other aspects. This Cost Function may be used to compare different approaches after an evaluation of the radio performance and the splitting of processing functions between the ASIC and the DSP. In particular, for sub optimal algorithms, the analysis for the DSP devices covers the evaluation of the number of required MIPS for both C5000 and C6000 families, the number and the type of peripherals involved and the memory utilization. The optimization of the sub optimal design may be obtained by refining both the algorithms and the ASIC-DSP functions assignment.

Last update: 2014-11-15, 00:22:18