Professional DVB-T receiver
A winning choice
This information sheet treats the design of base-band processing subsystems for professional DVB-T receivers based on Texas Instruments TMS320C6000 fixed point DSPs. The adoption of general purpose DSPs make this receiver the unique Software Radio Receiver for DVB-T system and grant a large flexibility in the development of different configurations of the receiver.
The 16/32 bit fixed point architecture of TI C6000 device family leads to a very low implementation loss, and a careful optimization of the processor pipeline architecture allows the receiver to obtain short processing delays. Furthermore, it enables the feasibility of adaptive equalization schemes, where the quality of the channel estimation varies according to both frequency selective and fast fading channel.
The capability to pick-up the signal at each stage throughout the receiver chain, enables it providing a lot of signal and channel measurements at the receiver side.
These features, combined with the flexibility of the software approach, along with the obtained performance, make the proposed implementation very interesting in broadcasting and high-end receivers for interactive, multimedia and research applications of DVB-T.
Our DVB-T receiver system block diagram is presented in figure 1, from which it is evident that the main receiver functional operations are based on DSPs. Just convolutional deinterleaver and channel decoding are realized on FPGA and ASIC devices, allowing any future developments without hardware redesign.
In particular the present design includes:
- Two 12 bit fast A/D converters for I and Q signal base-band components, with sample rate of 9.14 Msamples/s.
- Five DSPs, in particular:
- DSP-1 for OFDM symbol and frequency synchronization.
- DSP-2 for OFDM demodulation.
- DSP-3 for Common Phase Error correction.
- DSP-4 for Channel estimation and equalization.
- DSP-5 for QAM demapping and Channel State Information processing.
All the designed functional block are optimized to obtain state of the art performance; in particular, main features and performance are summarized below:
- The synchronization block exhibits performance very close to an ideal implementation using floating point arithmetic and guarantees appropriate signal acquisition for low values of SNR also in critical channel conditions as in SFN (see figure 2).
- The DVB-T demodulator is characterized by an SQNR greater than 50 dB in the 8k mode and greater than 56 dB in the 2k mode with a processing time respectively of 857ms and 174ms for all the OFDM symbols (no pipeline design is used, see figure 3).
- The DVB-T equalizer is adaptive to face both SFN static and MFN mobile reception conditions. It is able to manage a channel dynamic range up to 64 dB with near to floating point performance obtained with a smart division algorithm for the channel inversion (see figure 4).
- The processing of the Channel State Information allows it achieving a true soft decision Viterbi decoding with a performance gain (in terms of BER) of more than 1 dB for Ricean Channels and up to 4 dB for Raleigh and SFN channels with respect to the performance predicted in the DVB-T standard (see figure 5).
Our DVB-T receiver is ETSI standard En-300-744 v1.1.2 compliant and it is based on a PCI board architecture,
according with diagram presented in figure 6, in which, compared to figure 1, some devices are been added to perform fixed tasks as deinterleving and channel decoding according. In detail:
- FPGA for symbol and bit deinterleaver (designed for Soft Viterbi decoding).
- ASIC for channel decoding (Soft Viterbi and Reed-Solomon decoding).
- A FIFO RAM is used as interface between the 12 bit A/D converters and the DSP-1.
- FOUR banks of SBSRAM are adopted to provide interface among the other functional blocks.
- A MICROCONTROLLER manages the boot process and synchronizes the DSP operations via the interrupt signaling.
Figure 7 shows the main features of the receiver. This professional instrument is based on a common PC with a large LCD screen to provide the interface toward the operator by means of a Windows environment in which measurement diagrams and setting dialog windows are shown. Nevertheless, main commands can also be issued by the front panel on the right of the main display. An internal hard disk allows it recording measurements results and an Ethernet card interface connects this instrument to a LAN. A floppy disk (or a 120 MB disk) should also be provided to allow system reconfiguration and/or software updates and to record measurement results for further analysis.
In the High-End version a 16:9 LCD display is also available so you can control image quality simultaneously with received signal measurements to determine the low limits for received SNR to grant a good DVB-T service. Figure 8 is a summary of our DVB-T professional receiver characteristics, describing all the possible OUTPUT INTERFACES and MEASUREMENTS, CONFIGURATIONS and CONTROLS compatible with the hardware design.